Intel(R) Threading Building Blocks Doxygen Documentation
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17 #if !defined(__TBB_machine_H) || defined(__TBB_machine_linux_ia32_H)
18 #error Do not #include this internal file directly; use public TBB headers instead.
21 #define __TBB_machine_linux_ia32_H
26 #define __TBB_WORDSIZE 4
27 #define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE
29 #define __TBB_compiler_fence() __asm__ __volatile__("": : :"memory")
30 #define __TBB_control_consistency_helper() __TBB_compiler_fence()
31 #define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
32 #define __TBB_release_consistency_helper() __TBB_compiler_fence()
33 #define __TBB_full_memory_fence() __asm__ __volatile__("mfence": : :"memory")
35 #if __TBB_ICC_ASM_VOLATILE_BROKEN
36 #define __TBB_VOLATILE
38 #define __TBB_VOLATILE volatile
41 #define __TBB_MACHINE_DEFINE_ATOMICS(S,T,X,R) \
42 static inline T __TBB_machine_cmpswp##S (volatile void *ptr, T value, T comparand ) \
46 __asm__ __volatile__("lock\ncmpxchg" X " %2,%1" \
47 : "=a"(result), "=m"(*(__TBB_VOLATILE T*)ptr) \
48 : "q"(value), "0"(comparand), "m"(*(__TBB_VOLATILE T*)ptr) \
53 static inline T __TBB_machine_fetchadd##S(volatile void *ptr, T addend) \
56 __asm__ __volatile__("lock\nxadd" X " %0,%1" \
57 : R (result), "=m"(*(__TBB_VOLATILE T*)ptr) \
58 : "0"(addend), "m"(*(__TBB_VOLATILE T*)ptr) \
63 static inline T __TBB_machine_fetchstore##S(volatile void *ptr, T value) \
66 __asm__ __volatile__("lock\nxchg" X " %0,%1" \
67 : R (result), "=m"(*(__TBB_VOLATILE T*)ptr) \
68 : "0"(value), "m"(*(__TBB_VOLATILE T*)ptr) \
78 #pragma warning( push )
80 #pragma warning( disable: 998 )
83 #if __TBB_GCC_CAS8_BUILTIN_INLINING_BROKEN
84 #define __TBB_IA32_CAS8_NOINLINE __attribute__ ((noinline))
86 #define __TBB_IA32_CAS8_NOINLINE
91 #if (__TBB_GCC_BUILTIN_ATOMICS_PRESENT || (__TBB_GCC_VERSION >= 40102)) && !__TBB_GCC_64BIT_ATOMIC_BUILTINS_BROKEN
92 return __sync_val_compare_and_swap(
reinterpret_cast<volatile int64_t*
>(ptr), comparand,
value );
105 __asm__ __volatile__ (
109 "lock\n\t cmpxchg8b %1\n\t"
111 "lock\n\t cmpxchg8b (%3)\n\t"
123 ,
"m"(i32[0]),
"c"(i32[1])
130 __asm__ __volatile__ (
131 "lock\n\t cmpxchg8b %1\n\t"
135 ,
"b"(i32[0]),
"c"(i32[1])
143 #undef __TBB_IA32_CAS8_NOINLINE
146 #pragma warning( pop )
147 #endif // warning 998 is back
150 __asm__ __volatile__(
"lock\norl %1,%0" :
"=m"(*(
__TBB_VOLATILE uint32_t *)ptr) :
"r"(addend),
"m"(*(
__TBB_VOLATILE uint32_t *)ptr) :
"memory");
154 __asm__ __volatile__(
"lock\nandl %1,%0" :
"=m"(*(
__TBB_VOLATILE uint32_t *)ptr) :
"r"(addend),
"m"(*(
__TBB_VOLATILE uint32_t *)ptr) :
"memory");
162 #define __TBB_fildq "fildll"
163 #define __TBB_fistpq "fistpll"
165 #define __TBB_fildq "fildq"
166 #define __TBB_fistpq "fistpq"
185 #if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
189 #if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
203 #if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
207 #if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
210 #if TBB_USE_PERFORMANCE_WARNINGS
219 #define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
220 #define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
222 #define __TBB_USE_GENERIC_DWORD_FETCH_ADD 1
223 #define __TBB_USE_GENERIC_DWORD_FETCH_STORE 1
224 #define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE 1
225 #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
226 #define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
227 #define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
#define __TBB_ASSERT(predicate, comment)
No-op version of __TBB_ASSERT.
#define __TBB_IA32_CAS8_NOINLINE
static int64_t __TBB_machine_load8(const volatile void *ptr)
static int64_t __TBB_machine_aligned_load8(const volatile void *ptr)
bool is_aligned(T *pointer, uintptr_t alignment)
A function to check if passed in pointer is aligned on a specific border.
static __TBB_IA32_CAS8_NOINLINE int64_t __TBB_machine_cmpswp8(volatile void *ptr, int64_t value, int64_t comparand)
void __TBB_machine_store8_slow(volatile void *ptr, int64_t value)
Handles misaligned 8-byte store.
void __TBB_machine_store8_slow_perf_warning(volatile void *ptr)
static void __TBB_machine_store8(volatile void *ptr, int64_t value)
void const char const char int ITT_FORMAT __itt_group_sync x void const char ITT_FORMAT __itt_group_sync s void ITT_FORMAT __itt_group_sync p void ITT_FORMAT p void ITT_FORMAT p no args __itt_suppress_mode_t unsigned int void size_t ITT_FORMAT d void ITT_FORMAT p void ITT_FORMAT p __itt_model_site __itt_model_site_instance ITT_FORMAT p __itt_model_task __itt_model_task_instance ITT_FORMAT p void ITT_FORMAT p void ITT_FORMAT p void size_t ITT_FORMAT d void ITT_FORMAT p const wchar_t ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s no args void ITT_FORMAT p size_t ITT_FORMAT d no args const wchar_t const wchar_t ITT_FORMAT s __itt_heap_function void size_t int ITT_FORMAT d __itt_heap_function void ITT_FORMAT p __itt_heap_function void void size_t int ITT_FORMAT d no args no args unsigned int ITT_FORMAT u const __itt_domain __itt_id ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain __itt_id ITT_FORMAT p const __itt_domain __itt_id __itt_timestamp __itt_timestamp ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain ITT_FORMAT p const __itt_domain __itt_string_handle unsigned long long value
static void __TBB_machine_aligned_store8(volatile void *ptr, int64_t value)
#define __TBB_MACHINE_DEFINE_ATOMICS(S, T, X, R)
static void __TBB_machine_or(volatile void *ptr, uint32_t addend)
static void __TBB_machine_and(volatile void *ptr, uint32_t addend)
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