Intel(R) Threading Building Blocks Doxygen Documentation
version 4.2.3
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#include "gcc_ia32_common.h"
Go to the source code of this file.
Classes | |
struct | tbb::internal::machine_load_store< T, S > |
struct | tbb::internal::machine_load_store_relaxed< T, S > |
struct | tbb::internal::machine_load_store_seq_cst< T, S > |
Namespaces | |
tbb | |
The graph class. | |
tbb::internal | |
Identifiers declared inside namespace internal should never be used directly by client code. | |
tbb::internal::icc_intrinsics_port | |
Macros | |
#define | __TBB_WORDSIZE 8 |
#define | __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE |
#define | __TBB_compiler_fence() __asm__ __volatile__("": : :"memory") |
#define | __TBB_full_memory_fence() __asm__ __volatile__("mfence": : :"memory") |
#define | __TBB_control_consistency_helper() __TBB_compiler_fence() |
#define | __TBB_MACHINE_DEFINE_ATOMICS(S, T, M) |
#define | __TBB_USE_FENCED_ATOMICS 1 |
Typedefs | |
typedef enum tbb::internal::memory_order | tbb::internal::memory_order |
typedef enum tbb::internal::icc_intrinsics_port::memory_order_map | tbb::internal::icc_intrinsics_port::memory_order_map |
Enumerations | |
enum | tbb::internal::memory_order { tbb::internal::memory_order_relaxed, tbb::internal::memory_order_consume, tbb::internal::memory_order_acquire, tbb::internal::memory_order_release, tbb::internal::memory_order_acq_rel, tbb::internal::memory_order_seq_cst } |
enum | tbb::internal::icc_intrinsics_port::memory_order_map { tbb::internal::icc_intrinsics_port::relaxed = memory_order_relaxed, tbb::internal::icc_intrinsics_port::acquire = memory_order_acquire, tbb::internal::icc_intrinsics_port::release = memory_order_release, tbb::internal::icc_intrinsics_port::full_fence = memory_order_seq_cst } |
Functions | |
template<typename T > | |
T | tbb::internal::icc_intrinsics_port::convert_argument (T value) |
template<typename T > | |
void * | tbb::internal::icc_intrinsics_port::convert_argument (T *value) |
template<typename T > | |
void | __TBB_machine_OR (T *operand, T addend) |
template<typename T > | |
void | __TBB_machine_AND (T *operand, T addend) |
#define __TBB_compiler_fence | ( | ) | __asm__ __volatile__("": : :"memory") |
Definition at line 51 of file icc_generic.h.
#define __TBB_control_consistency_helper | ( | ) | __TBB_compiler_fence() |
Definition at line 66 of file icc_generic.h.
#define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE |
Definition at line 42 of file icc_generic.h.
#define __TBB_full_memory_fence | ( | ) | __asm__ __volatile__("mfence": : :"memory") |
Definition at line 61 of file icc_generic.h.
#define __TBB_MACHINE_DEFINE_ATOMICS | ( | S, | |
T, | |||
M | |||
) |
Definition at line 135 of file icc_generic.h.
#define __TBB_USE_FENCED_ATOMICS 1 |
Definition at line 177 of file icc_generic.h.
#define __TBB_WORDSIZE 8 |
Definition at line 40 of file icc_generic.h.
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inline |
Definition at line 255 of file icc_generic.h.
References tbb::internal::memory_order_seq_cst.
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inline |
Definition at line 250 of file icc_generic.h.
References tbb::internal::memory_order_seq_cst.